1. Technical Field of the Invention
This invention most generally relates to software tools, packages, programs and algorithms used for predicting the outcome and assisting in the performance of a given task or sequence of tasks, by emulating the task or sequence of tasks. In particular, it relates to analytical tools used in the process of designing the hardware and software components of an integrated circuit or printed circuit board.
2. Background Art
The current design process for creating integrated circuit (IC) production designs for digital circuits is linear in the sense that there is little concurrence among or iteration of the constituent steps. The process is executed one step at a time. The final step evaluates and verifies the quality of the design. If the design does not meet design goals and manufacturing criteria, then the process is iterated either in its entirety or at the latest possible step.
At a very high level, the process proceeds according to FIG. 1, where Element A, "capture", represents the step or phase where schematic or language-based electrical functionality VHDL/Verilog) is captured and electrically simulated at the functional block or cell level, showing block/cell properties and interconnects. Element B, "synthesis", represents the next step or phase where the "register transfer level" (RTL) logical implementation of each block or cell is created.
Element C, "floorplan/placement", represents the step or phase where blocks/cells are physically implemented and maneuvered relative to each other within an outline drawing representation of the IC. Element D, "routing", represents the next step or phase where interconnects are physically implemented, based on floorplan/placement data and other specified constraints.
Element E, "analysis", represents the step where electrical properties are extracted from the physical design and compared to block/cell properties and assumptions or constraints adopted in previous steps. Element F, "tape out", represents the step or phase where agreement between logical and physical design is verified, and the data converted to a format compatible with the user's IC manufacturing capability.
Expanding further on the conventional process of FIG. 1, we examine the first step in the process called capture. In this step, the design is first captured as electrical components and wires displayed schematically or as a "blue print". This is a logical or conceptual representation of the IC, rather than a physical design, which shows the various subsections of the design (cells and/or blocks), annotates or describes various properties of theses subsections (for documentation purposes or for subsequent steps in the design process), and the electrical connections which will be formed (routed) between subsections. The capture phase includes the use of many simulation tools to help predict parametric, functional, and/or behavioral IC performance.
As the cells and blocks are added to the schematic and individually instantiated and annotated, nets are added which tie the various pins of the cells/blocks to each other or to pads (inputs/outputs of the chip itself).
The second step of the process is also part of the logical design phase. Synthesis is the taking of the high level representation of the circuit and transforming it into a lower level which is optimized for any of several criteria, such as speed or size. The lower level is usually referred to as RTL, or register transfer level. Synthesis tools attempt to fully automate the generation of the lower level description from the higher level description.
These first two steps comprise the logical phase of the design process. There is no direct link in this phase to anything which is actually manufactured. Extensive simulation of the logical design is performed against important electrical, thermal, and other parametric, functional, or behavioral criteria.
Placement is the first step which involves physical realization of the design. The various components captured and synthesized are placed as cells and blocks relative to each other and the pads. Placement optimizes the positioning of each cell/block to reduce chip size and to meet thermal and routing constraints.
Routing is the final step of the physical realization phase. Whereas placement corresponded to the placing of blocks/cells on the schematic, routing is the realization of the nets. Routing is also constrained by criteria such as type of route (power, ground, signal rip) and the criticality of a route. Insufficient or excessive room on the chip for a complete routing usually requires iteration of the placement step. Routing software automates the generation of routes based on constraints defined by all previous steps of the design process.
After the physical design is fully realized, it is analyzed to make certain that it matches logical, simulated performance. The analysis can also be used to validate any assumptions made during any previous phase of the entire design process. Unsatisfactory analysis results require the further iteration of one or all design steps. Successful analysis leads to final verification and then to tape out for manufacturing.
The major problem with the conventional design methodology is that information essential to a successful, single (first) pass design is usually not available to the logical designer until much later in the design process. Simply stated, the design process can not be fully captured logically without first realizing it physically. In practice, the analysis step reveals that various design objectives and assumptions had to be violated to get a realizable design; the design does not fully comply with the original goals or specifications. All or part of the design process must be repeated to modify the current design so that it is both physically realizable and specifically compliant.
An example of this maybe found in the myriad of Intel.RTM. Pentium.RTM. chips on the market, where we consider the design goal as the clock frequency. As the design process is completed, it is clear that the chip will work at a frequency less than that specified as the goal. While the chip is still manufactured and sold it can be used as the basis for a new design which may achieve the original frequency goal. While these derivative products often contribute to the product line revenue stream, a single iteration of a 100 person design team for a three month period can add millions of dollars to a project in direct labor costs. Lost market share because of late product entry can cost many times more.
This problem becomes much more acute with deep submicron (DSM) manufacturing technology. The smaller the features on an IC, the greater the number of cells/blocks and their complexity which can be added. Furthermore, smaller transistors correspond to faster transistors, albeit at a rate of diminishing returns.
The combination of more and faster transistors leads to a shift in how to calculate the time it takes an electrical input signal to manifest itself as an output. In pre-DSM designs, this input-output time, or delay, was calculated by adding up the number of transistors the signal went through and then adding a margin to account for the interconnects connecting the transistors. Interconnect delay dominates this equation in DSM designs, thus making it necessary to get through the routing step of the design (i.e. completing the entire design) process before the designer can determine the interconnect delay of any given net. The predominance of interconnect issues make it that much more difficult to fully appreciate the design without going through the routing step.
There is this notion, then, of uncertainty in the design. Engineers traditionally build in margin to account for these unknowns. In very aggressive manufacturing technologies, such margins cut into the performance enhancement offered by manufacturing but left unrealized by the design. Interconnect delay has been treated as something which was not necessarily considered fully, but rather something for which you built in margin.
Power dissipation is a similar concern and its consideration at each step of the design process is essential to a DSM design with minimal iteration. At a higher level, designers would also like to make similar trade-offs between what should be in hardware, software, and firmware as well as hardware architectures. All of these design considerations require constraints at early design steps based on limited information as to the results of latter steps.
Exacerbating these problems is the fact that no one person can perform and excel at the entire design process. Thus, two subgroups have arisen out of the design team--logical (circuit) engineers and physical (design) engineers. This division potentially impedes the design flow because of data transfer issues as well as those associated with group dynamics.